A High-Power Ku-Band PA Using Multi-Combiner Architecture

This paper presents a Ku-band multi-combined power amplifier (PA) implemented in 130-nm CMOS SOI technology for LEO satellite communication phased arrays. To overcome CMOS integration challenges while attaining watt-level output, the design incorporates two key techniques: a triple-cascode topology and a low-loss, multi-stage power combiner. The triple-cascode structure utilizes RF-grounded symmetrical stacking to eliminate external gate capacitors, thereby enhancing voltage gain, output power, and robustness against input imbalance. The multi-stage combiner efficiently aggregates power from 32 unit cells by integrating four-way transformers with strip-line and transmission-line networks, achieving low insertion loss within a compact footprint. Experimental results show a 3-dB bandwidth of 10.5–14.5 GHz, a saturated output power (Psat) of 30.8 dBm (1.2 W), and a peak power-added efficiency (PAE) of 19.9%. The proposed PA achieves superior output power among state-of-the-art 8–18 GHz CMOS PAs, demonstrating its strong potential for next-generation space-borne transmitters.