Performance Investigation of HfOX-Based 1-Transistor–1-Memristor Cell for In-Memory Logic Gates Implementation

The transistor–memristor (1T-1M) integration has been recognized as an effective strategy to suppress crosstalk between neighboring cells for the development of a practical crossbar architecture, though its adoption for in-memory Boolean logic gate implementation is still missing. In this regard, we systematically investigate HfOX-based 1T-1M cell for in-memory logic gates implementation employing the Memristor-Aided loGIC (MAGIC) design style. This performance analysis is carried out using a fully calibrated and physics-based Stanford-PKU model, which captures full I–V switching dynamics, including temperature and stochastic effects. Our results show that the 1T-1M cell with the Gate and Source-controlled Off-State RESET (GSOSR) scheme substantially increases the high resistance state (HRS), which enables nearly $2.2\times $ higher on-off resistance ratio compared to the 1M cell and achieves significant energy saving in execution operation for AND, NAND, XOR, and XNOR gates. Despite the 1T-1M cell exhibiting a slight increase in delay due to additional capacitances, the associated energy reduction and improved reliability outweigh this penalty. Variability analysis further reveals that the XOR gate with 1T-1M cell suppresses resistance fluctuation in both low resistance state (LRS) and HRS by up to $3\times $ under worst-case corners, which ensures more robust operation over 1M cell. Overall, our findings demonstrate that the 1T-1M cell offers a viable path toward a scalable, energy-efficient, robust, and crossbar-compatible in-memory computing system, surpassing the widely employed 1M cell architecture.