A 16× Interleaved 32-GS/s 8b Hybrid ADC With Self-Tracking Inter-Stage Gain Achieving 44.3-dB SFDR at 20.9-GHz Input

This article presents a 32-GS/s 16-channel hierarchical time-interleaved (TI) hybrid analog-to-digital converter (ADC). The prototype utilizes the intrinsic high-speed quantization of time-domain (TD) ADC to reduce the interleaving factor. By incorporating hierarchical sampling and a cascode sampler, the compact TI-ADC achieves 44.3-dB spurious-free dynamic range (SFDR) at 20.9-GHz input. The sub-ADC adopts a two-stage hybrid-domain architecture that combines a 3-bit successive approximation register (SAR) ADC with a 6-bit inverter-based opposite phase propagation (OPP) time-to-digital converter (TDC). Aprototype chip is fabricated in a 28-nm CMOS process, occupying a core area of 0.141mm<sup xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink">2</sup>. At 32GS/s, it achieves a signal-to-noise and distortion ratio (SNDR) of 36dB with a Nyquist input while consuming 142.3mW, corresponding to a Walden figure-of-merit of 86.3fJ/conv-step. Meanwhile, a delay-locked loop (DLL)-based calibration loop is proposed to calibrate the full-scale quantization range variation introduced by PVT variations, together with an analog self-tracking inter-stage gain calibration loop. The measured SNDR varies by 1.84dB over a temperature range of <inline-formula xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink"> <tex-math notation="LaTeX">$0~{^{\circ } }$</tex-math> </inline-formula>C to <inline-formula xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink"> <tex-math notation="LaTeX">$100~{^{\circ } }$</tex-math> </inline-formula>C and fluctuates by 2.25dB with a ±10% supply variation.