EngineeringMedicine

Yili Shen, Yekan Chen, Changgui Yang, Tingting He, Chaonan Yu, Jun Zhou, Yuxuan Luo, Kedi Xu, Gang Pan, Yunshan Zhang, Bo Zhao

2026.4.10IEEE Transactions on Biomedical Circuits and Systems

DOI: 10.1109/tbcas.2026.3683086

Abstract

Multi-channel neural recording enables simultaneous monitoring of neuronal activities across multiple brain regions, while the in-vivo common-mode interference (CMI) significantly degrades the signal quality of implantable neural-recording chips. For a multi-channel neural-recording chip, the total common-mode rejection ratio (T-CMRR) of the analog front-end (AFE) is limited by the input imbalance between the signal electrode and the shared reference electrode, as well as the intrinsic CMRR (I-CMRR) of its circuits. The traditional common-mode replication (CM-REP) technique is only applicable to single-channel systems such as ECG monitoring devices. In addition, conventional pre-amplifier and frequency-controlled differential regulator (FCDR) techniques suffer from gain mismatch and high power consumption, respectively. To address these issues, this work presents a 32-channel neural-recording chip fabricated in a 65 nm CMOS process, which effectively suppresses the CMI in two operational modes: 1) In high-gain mode, the proposed CM-tracking-dynamic-power-rail (CM-TDPR) instrumentation amplifier (IA) achieves 50 GΩ CM input impedance, 117 dB I-CMRR, and 100 dB power supply rejection ratio (PSRR), resulting in a T-CMRR of 87 dB; 2) In low-gain mode, a CM-canceling-in-idle-phase (CM-CIP) technique is proposed to increase the I-CMRR to 102 dB and match the signal-reference input impedance, thereby achieving a 95 dB T-CMRR. In-vivo experiments were conducted on a Sprague-Dawley rat, successfully validating the CMRR performance of the proposed chip.

Citation format

SHEN, Yili, et al. A 32-channel neural-recording chip achieving 117db intrinsic-cmrr and 100db PSRR by CM-Tracking-Dynamic-Power-Rail and CM-Canceling-in-Idle-Phase techniques. IEEE Transactions on Biomedical Circuits and Systems, 2026, PP: 1–15.