VLA-TAGE: A Power-Efficient Branch Predictor With Vector-Loop Awareness

Data-parallel workloads, such as machine learning, computer vision, and data analytics, increasingly run on mobile SoCs (System on Chip) with SIMD (Single Instruction, Multiple Data) engines to provide real-time user interactions and security. It is crucial to design processor architectures that balance high performance and power efficiency. In this paper, we make the key observation that these data-parallel workloads exhibit regular, predictable control flow, reducing the need for complex branch prediction mechanisms. However, state-of-the-art predictors like TAGE incur substantial power overhead due to multi-table lookups. In SIMD-intensive regions with long, regular loops, simpler prediction schemes can achieve comparable accuracy. Based on this insight, we propose Vector-Loop-Aware TAGE(VLA-TAGE), using a lightweight mechanism that dynamically gates access to TAGE tables during predictable SIMD execution while restoring full functionality for irregular control flow. VLA-TAGE maintains accuracy comparable to TAGE-SC-L while reducing the number of history table accesses by an average of 63%, resulting in a 51% reduction in power consumption on data-parallel workloads.