GeoSynth: Constraint-Aware Automation for Scalable Superconducting Quantum Chip Design

As superconducting quantum processors scale beyond thousands of qubits, manual layout methods pose the primary bottleneck to industrial deployment. Traditional quantum electronic design automation (EDA) tools emphasize component-level modeling but lack full-chip integration for scalable systems. This work formulates scalable superconducting quantum chip design as a geometric constraint satisfaction problem (CSP) and introduces GeoSynth, a constraint-aware automation framework to accelerate scalable quantum chip design. By leveraging global symmetry and local similarity of quantum chip, GeoSynth enables hierarchical constraint decomposition through four novel algorithms: adaptive launch pad allocation (GeoSynth-ALA), systematic component correspondence (GeoSynth-SCC), scalable template-based routing synthesis (GeoSynth-TRS), and global constraint propagation (GeoSynth-GCP). Implemented in EDA-Q, GeoSynth delivers an end-to-end automation flow for a 156-qubit flip-chip processor in 2,882 seconds. This represents a 2× speedup over a prior method that addressed only the routing subproblem for 64 qubits, and is crowned by the first fabrication validation of an automatically generated large-scale layout, achieving a T1 coherence time of 69.24 μs. Beyond fabrication validation, GeoSynth demonstrates robust scalability by successfully generating layouts for diverse configurations spanning 64 to 620 qubits across multiple architectural variants, confirming its capability to handle industrially relevant scales. GeoSynth’s efficient, constraint-driven automation offers a scalable solution for quantum hardware industrialization.