A Sub-20 mV VTH Hysteresis Enhancement-Mode GaN p-FET With PEALD AlON Gate Dielectric

Large threshold voltage (<inline-formula> <tex-math notation="LaTeX">${V}_{\text {TH}}\text {)}$ </tex-math></inline-formula> hysteresis in GaN <inline-formula> <tex-math notation="LaTeX">$p$ </tex-math></inline-formula>-channel heterojunction field-effect transistors (<inline-formula> <tex-math notation="LaTeX">$p$ </tex-math></inline-formula>-FETs) significantly degrade device performance and limit its complementary circuit integration potential. This letter reduces the <inline-formula> <tex-math notation="LaTeX">${V}_{\text {TH}}$ </tex-math></inline-formula> hysteresis of enhancement-mode (E-mode) GaN <inline-formula> <tex-math notation="LaTeX">$p$ </tex-math></inline-formula>-FETs to 20 mV by employing a novel plasma-enhanced atomic layer deposition (PEALD)-grown AlON gate dielectric. Compared to <inline-formula> <tex-math notation="LaTeX">$p$ </tex-math></inline-formula>-FET with Al₂O₃ gate dielectric, a 15 nm PEALD AlON improved hysteresis from 4.1 V to sub-20 mV under dual-sweep dc-mode measurement. Furthermore, the fabricated E-mode <inline-formula> <tex-math notation="LaTeX">$p$ </tex-math></inline-formula>-FETs with AlON and Al₂O₃ gate dielectrics achieve ON-resistance (<inline-formula> <tex-math notation="LaTeX">${R}_{\text {ON}}\text {)}$ </tex-math></inline-formula> of <inline-formula> <tex-math notation="LaTeX">$670~\Omega \cdot $ </tex-math></inline-formula>mm and <inline-formula> <tex-math notation="LaTeX">$1268~\Omega \cdot $ </tex-math></inline-formula>mm, and ON-state current (<inline-formula> <tex-math notation="LaTeX">${I}_{\text {ON}}\text {)}$ </tex-math></inline-formula> of 8.2 mA/mm and 2.8 mA/mm, respectively. The novel AlON dielectric provides significant opportunities for developing GaN complementary circuit integration.