Fault detection scheme for negative control flipping faults in reversible circuits

Today?s the CMOS technologies-based electronic devices are designed to be comprised of numerously efficient microchips to meet the demands of fast computational power, and there is a need to perform loss-less information computation. In this context, the reversible logic way of computation is a rapidly growing research area for low-power circuit design and lossless information computation. The conceptual reversible computation is widely applied in current technologies, such as quantum computing. The analysis and efficient functioning of the reversible logic depended on the various domains, such as reversible logic synthesis, verification, testing, and debugging. This article focuses on the domain of testing reversible logic circuits, which then examines a fault model referred to as the negative control flipping fault (NCFF) under the control flipping fault (CFF) model. In this paper, the proposed work necessitates the utilization of an automatic test pattern generation (ATPG) algorithm to generate a complete test set for detecting NCFFs. Moreover, the present work shows the correlation of NCFF with the existing fault models in reversible circuits by encompassing single missing gate fault (SMGF), multiple missing gate fault (MMGF), and partial missing gate fault (PMGF). Finally, experimental results are performed on several benchmark circuits to verify our proposed algorithm for fault detection of NCFF. Additionally, we have assessed the fault coverage capabilities of the existing fault models in reversible circuits with the help of a generated complete test set for NCFF in reversible circuits.