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Computer ScienceEngineering

FPGA-based hardware accelerator designed for convolutional residual spiking neural networks

Yahui Zhang, S. Xiang, Chenyang Du, Tao Zou, Xingxing Guo, Ling Zheng, Licun Yu, Genquan Han, Y. Hao

2026.1.22Science China-Information Sciences

DOI: 10.1007/s11432-025-4686-2

Abstract

Abstract is not available.

Citation format

ZHANG, Yahui, et al. FPGA-based hardware accelerator designed for convolutional residual spiking neural networks. Science China-Information Sciences, 2026, 69(3).