Subtractive Microfluidics in CMOS

This paper introduces a microfluidics platform embedded within a silicon chip implemented in CMOS technology. The platform utilizes a one-step wet etching method to create fluidic channels by selectively removing CMOS back-end-of-line (BEOL) routing metals. We term our technique “subtractive” microfluidics, to complement those fabricated with additive manufacturing. Three types of structures are presented in a TSMC I80-nm CMOS chip: (1) passive microfluidics in the form of a micro-mixer and a 1: 64 splitter, (2) fluidic channels with embedded ion-sensitive field-effect transistors (ISFETs) and Hall sensors, and (3) integrated on-chip impedance-sensing readout circuits including voltage drivers and a fully differential transimpedance amplifier (TIA). Sensors and transistors are functional pre-and post-etching with minimal changes in performance. Our CMOS subtractive microfluidics technique enables tight integration of fluidics and electronics, paving the way for future small-size, high-throughput lab-on-chip (LOC) devices.