A High Linear CMOS PA Using a Weighted Distributed Enhanced Transformer Phase‐Delayed Group Linearizer at 77 GHz

This paper presents a W‐band two‐way four‐stage power amplifier (PA) implemented in 28‐nm CMOS technology, featuring a novel weighted distributed enhanced group linearizer (WDE‐GL). The proposed WDE‐GL architecture incorporates three stages, each operating at a different power level along the signal path. This design enables compensation with different weights for each linearizer stage, optimizing the linear performance, particularly for high‐gain RF PAs. Each WDE‐GL stage employs an introduced transformer phase‐delayed reverse body‐biasing technique to reduce its insertion loss and improve its compensation slope, achieving an optimal trade‐off between linearity, efficiency, and gain. Furthermore, this approach supports stage‐specific activation, providing flexibility for high‐accuracy and eco‐friendly modes, making it well‐suited for automotive radar systems and electric vehicle applications. The implemented PA achieves, at 77 GHz, a maximum power added efficiency (PAE) of 11.7%, an output power at the 1‐dB compression point (OP 1dB ) of 13.8 dBm, and a saturated output power ( P sat ) of 15.7 dBm, utilizing a core area of 0.11 mm 2 . The WDE‐GL significantly enhances the linear behavior of the PA, reducing the amplitude‐to‐amplitude, amplitude‐to‐phase, and intermodulation distortions. It also increases the OP 1dB and its PAE by 3.4 dB and 4.5%, respectively. These improvements represent enhancements of 120% and 83% compared with the deactivated WDE‐GL case, marking the best reported performance for W‐band PAs.