Photolithography-Compatible Low-Voltage OTFT Enabled by a Trilayer Dielectric Design With PDK-Compatible Development

Organic thin-film circuit design requires not only high-performance transistors but also reproducible device behavior that can be captured in compact models and supported by a process design kit (PDK). Existing low-voltage organic thin-film transistors (OTFTs) technologies often rely on shadow-mask or printed process, where coarse patterning and alignment variability hinder device uniformity, parasitic management, and integration scalability. This work presents a photolithography-compatible OTFT platform based on a trilayer dielectric stack that achieves uniform, low-voltage transistor operation with a mobility of <inline-formula> <tex-math notation="LaTeX">$0.87~\pm ~0.07$ </tex-math></inline-formula> cm²V<inline-formula> <tex-math notation="LaTeX">${}^{-{1}}$ </tex-math></inline-formula> s<inline-formula> <tex-math notation="LaTeX">${}^{-{1}}$ </tex-math></inline-formula>, a threshold-voltage of <inline-formula> <tex-math notation="LaTeX">$0.96~\pm ~0.13$ </tex-math></inline-formula> V and an 87% functional yield across the substrate. These reproducible device characteristics enable the extraction of a calibrated Level-62 RPI poly-TFT compact model, which is integrated into a complete PDK with defined layers, routing modules, and verified design-rule check (DRC)/layout-versus-schematic (LVS) rules. Circuit demonstrations, including inverters, nand gates, a leader–follower D-flip-flop (DFF), and a full adder, reproduce the expected Boolean functionality under low-voltage operation. The results establish a unified workflow that links lithography-defined OTFT fabrication with PDK-compatible modeling and circuit-level simulation, providing a foundation for scalable organic thin-film electronics.