Characterizing the Intrinsic Bank-Level Accuracy Versus Energy Trade-Off of SRAM-Based Analog In-Memory Computing Architectures in 28 nm CMOS

In-memory computing (IMC) architectures are emerging as the next-generation computing platforms for deep learning applications, surpassing traditional von Neumann architectures due to their superior energy efficiency and computational density. However, there is a lack of comprehensive understanding of the trade-off between accuracy at the bank level and energy consumption of SRAM-based IMCs, which execute computations in the analog domain. To gain a complete understanding of IMC’s fundamental limits and design space, we first adopt the signal-to-noise-and-distortion ratio (SNDR) as a metric, inspired by ADC design, to quantify the accuracy at the bank level. Second, we propose a methodology for accurately measuring SNDR. Finally, we propose a chip architecture for to directly measure pre-ADC SNDR. This characterization chip, incorporating mainstream IMC architectures, is fabricated in 28 nm CMOS technology. Measurement results indicate that SNDR and energy consumption are trade-offs that can be adjusted through the dot-product dimension and wordline voltage for charge/current summing models, and through input-driver voltage for a charge-redistribution model. To the best of our knowledge, this is the first experimental quantification of the trade-off between bank-level accuracy and energy consumption for SRAM-based IMC architectures through silicon measurements. These results underscore the importance of characterizing IMC SNDR to properly benchmark and compare future IMC designs.