PigMap2: A Physical Information-Guided Technology Mapping Framework

A typical very large scale integration (VLSI) design flow is divided into separate front-end logic synthesis and back-end physical design stages. This separation often necessitates time-consuming iterations between these stages to achieve closure on performance, power, and area metrics, which rely on physically aware synthesis methodologies. Existing approaches face significant challenges in two key areas: first, utilizing feedback from physical metrics to refine synthesis operations, and second, establishing comprehensive metrics that bridge the gap between logic synthesis and physical design. To address these limitations, this article introduces PigMap2, a novel technology mapping framework designed to integrate physical information into logic synthesis through intermediate representation (IR) placement. PigMap2 leverages placement-derived wirelength and congestion metrics to guide technology mapping, generating physical-design (PD)-friendly netlists. Key contributions include a fast IR placement algorithm, physically aware metrics, and a novel mapping algorithm. We evaluate our framework using the EPFL benchmark suite and IWLS’05 benchmark suite with ASAP7 technology, employing the OpenROAD tool for place-and-route. Compared with OpenROAD flow scripts, PigMap2 achieves a 13.4% overall PPA improvement over the current mapping flow and achieves 3.6% more improvement than the previous best mapping scheme of PigMap on EPFL benchmarks. PigMap2 also achieves a 23% improvement in WNS and a 34% improvement in power consumption while maintaining consistent area, compared with the default mapping flow of Yosys on the IWLS’05 benchmark suite.