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DELAY-POWER PERFORMANCE COMPARISON OF MULTIPLIERS IN VLSI CIRCUIT DESIGN

S. R. Vaidya, D. Dandekar

2010.7.9International Journal of Computer Networks and Communications

DOI: 10.5121/ijcnc.2010.2405

tlooto Summary

Comparison study of different multipliers of Ancient Indian Vedic Mathematics is done for low power requirement and high speed to improve the speed, area parameters of multipliers.

Abstract

Abstract is not available.

Citation format

VAIDYA, S. R.; DANDEKAR, D. DELAY-POWER PERFORMANCE COMPARISON OF MULTIPLIERS IN VLSI CIRCUIT DESIGN. International Journal of Computer Networks and Communications, 2010, 2: 47–56.