B. Chappell, Xinning Wang, Priyadarsan Patra, Prashant Saxena, J. Vendrell, Satyanarayan Gupta, S. Varadarajan, W. Gomes, S. Hussain, H. Krishnamurthy, M. Venkateshmurthy, S. Jain
2002.9.16Proceedings - IEEE International Conference on Computer Design: VLSI in Computers and Processors
tlooto Summary
The described optimization flow, abstraction modes, and key cost factors deliver power-optimized, noise-correct domino performance on complex logic.
Abstract
System structure and a taped out 0.18u 2 GHz product application result are described for a domino synthesis capability that covers all aspects of domino design, from estimation to silicon-ready layout, with custom-class optimization. The described optimization flow, abstraction modes, and key cost factors deliver power-optimized, noise-correct domino performance on complex logic.
Citation format
CHAPPELL, B., et al. A system-level solution to domino synthesis with 2 ghz application. Proceedings - IEEE International Conference on Computer Design: VLSI in Computers and Processors, 2002: 164–171.