Year-long 500°C Operational Demonstration of Up-scaled 4H-SiC JFET Integrated Circuits

This work describes recent progress in the design, processing, and testing of significantly up-scaled complex 500°C–durable 4H-SiC junction field effect transistor (JFET) integrated circuit (IC) technology with two-level interconnect undergoing development at NASA Glenn Research Center. For the first time, stable electrical operation of semiconductor ICs for more than 1 y at 500°C in an air atmosphere is reported. These groundbreaking durability results were attained on two-level interconnect JFET demonstration ICs with 175 or more transistors on each chip. This corresponds to a more than 7-fold increase in 500°C–durable circuit complexity from the 24-transistor ring oscillator ICs reported at HiTEC 2016. These results advance the technology foundation for realizing long-term durable 500°C ICs with increased functional capability for combustion engine sensing and control, planetary exploration, deep-well drilling monitoring, and other harsh-environment applications.