P.J. Cacharelis, M. Hart, M. Manley, S.O. Frake, M. Knecht
1988.12.11Technical Digest - International Electron Devices Meeting
tlooto Summary
A single-polysilicon CMOS process that has been optimized for the production of high-speed programmable logic devices (PLDs) is described, which is a modular addition to a standard CMOS logic process and uses a single- polysilicon EPROM cell.
Abstract
The authors describe a single-polysilicon CMOS process that has been optimized for the production of high-speed programmable logic devices (PLDs). The process departs from conventional approaches in two respects: it is a modular addition to a standard CMOS logic process, and it uses a single-polysilicon EPROM cell. The technology has been used to fabricate a 22F10 PLD with an access time of 9.0 ns. Snap-back has been identified as the major cause of program disturb.<<ETX>>
Citation format
CACHARELIS, P.J., et al. A modular 1 mu m CMOS single polysilicon EPROM PLD technology. Technical Digest - International Electron Devices Meeting, 1988: 60–63.