Asisa Kumar Panigrahy, Sudheer Hanumanthakari, Shridhar B. Devamane, S. Choubey, M. Prasad, D. Somasundaram, N. Kumareshan, N. Vignesh, Gnanasaravanan Subramaniam, Durga Prakash M, Raghunandan Swain
tlooto Summary
Researchers analyze a novel GAA Junction-less nanosheet FET for analog and RF applications at 30 nm regime, showing high transconductance and cut-off frequency.
Abstract
This research focuses on a quantum model created using an entirely novel nanosheet FET. The standard model describes the performance of a Gate-all-around (GAA) Junction-less (JL) nanosheet device with a gate dielectric of SiO<sub>2</sub> and HfO<sub>2</sub>, each having a thickness of 1 nm. The performance of both the classical and quantum models of the GAA nanosheet device is evaluated using the visual TCAD tool, which measures the <italic>I<sub>ON</sub></italic>, <italic>I<sub>OFF</sub></italic>, <italic>I<sub>ON</sub>/ I<sub>OFF</sub></italic>, threshold voltage, DIBL, gain parameters (g<sub>m</sub>, g<sub>d</sub>, A<sub>v</sub>), gate capacitance, and cut-off frequency (<italic>f<sub>T</sub></italic>). The device is suited for applications needing rapid switching since it has a low gate capacitance of the order of 10<sup>–18</sup>, according to the simulation results. A transconductance (g<sub>m</sub>) value of 21 µS and an impressive cut-off frequency of 9.03 GHz are displayed during device analysis. A detailed investigation has also been done into the P-type device response for the same device. Finally, the proposed GAA nanosheet device is used in the inverter model. The NSFET-based inverter, although having higher gate capacitance, has the shortest propagation latency.
Citation format
PANIGRAHY, Asisa Kumar, et al. Analysis of GAA junction less NS FET towards analog and RF applications at 30 nm regime. IEEE Open Journal of Nanotechnology, 2024, 5: 1–8.